1. Field of the Invention
The present invention relates to a semiconductor device of SOI (Silicon On Insulator) structure. More particularly, the invention relates to a semiconductor device that has a CMOS (Complementary Metal Oxide Semiconductor) logic circuit.
2. Description of the Related Art
In recent years, the components of the CMOS devices have become smaller as is demanded. To make the components smaller and enhance the operating efficiencies of the components, such as current drivability, so-called scale-down is carried out in accordance with prescribed scaling rules. When the scale-down is performed on any CMOS device, it should be performed also on the element region of the semiconductor substrate and on the element-isolating region of the substrate.
It is pointed out, however, that the performance of the CMOS device changes if the diffusion layers functioning as the source and drain regions of the MOS transistors formed in the element region are narrowed. This change in the performance of the CMOS device results from the stress applied to the element region from the insulators that are formed in the element-isolating region. More specifically, insulators may be embedded in the trenches m in the semiconductor substrate, thus achieving so-called STI (Shallow Trench Isolation). In this case, the insulators apply a compression stress to the element region. The stress changes the mobility of the electrons or holes that are moving in the MOS transistors formed in the element region. Consequently, the performance of the CMOS device will vary.
In the MOS devices available at present, the element region is made of Si and the element-isolating region is made of SiO2-based material such as TEOS (Tetra-Ethyl-Ortho-Silicate). The thermal expansion coefficient of SiO2 is smaller than that of the Si. Hence, the stress from the element-isolating region compresses the element region. That is, the element region is more compressed than the element-isolation region when both regions are cooled from the high heat-treatment temperature to room temperature. In other words, the element region receives a compressing stress from the element-isolating region.
The change in the performance of the MOS transistors, which is caused by the compression stress applied from the element-isolating region, depends on the distance from the element-isolating region, or from either edge of the element region. The characteristics of P-type MOS transistors (hereinafter referred to as PMOS transistors) are inverse to those of the N-type MOS transistors (hereinafter referred to as NMOS transistors), depending on the distance from either edge of the element region. FIG. 50 shows a relation between current drivability and distance from either edge of the element region, for PMOS transistors and NMOS transistors. In FIG. 50, plotted on the horizontal axis is the distance X between the edge of the element region and the gate electrode of each transistor is plotted on the horizontal axis. Plotted on the vertical axis is the ratio ΔIdr of the current drivability of a transistor formed in an element region having a compression stress to that of a transistor formed in an element region having no compression stress. The ratio ΔIdr is 0% when the transistor in the element region with a compression stress has the same current drivability as the transistor in the element region with no compression stress. As evident from FIG. 50, the closer a PMOS transistor is to the edge of the element region, the higher its current drivability. By contrast, the farther a NMOS transistor is to the edge of the element region, the higher its current drivability.
A conventional CMOS device will be described. FIG. 51 is a plan view of an inverter circuit. The semiconductor substrate has two element regions 34 and 35. An element-isolating region 35 surrounds the element region 34. Five gate electrodes 37 are provided on the element region 34. A source and a drain are formed in the two parts of the element region 34, which lie on two sides of each gate electrode 37. Hence, five PMOS transistors PM1 to PM5 are provided in the element region 34. On the element region 35, three gate electrodes 38 are provided. A source and a drain are formed in the two parts of the element region 35, which lie on two sides of each gate electrode 38. Thus, three NMOS transistors NM1 to NM3 are provided in the element region 35.
The gate electrodes 37 and 38 are connected to the input unit IN. The source and drain of each transistor are connected to the power-supply voltage Vdd, the ground voltage gnd, or the output unit OUT. The inverter circuit is thus configured.
In the inverter circuit of FIG. 51, the PMOS transistors are formed in one element region and the NMOS transistors are formed in another element region. In whichever element region they are formed, the transistors differ in current drivability, in accordance with how far they are located from either edge of the element region.
Note that the current drivability of any PMOS transistor is opposite to that of any NMOS transistor and depends on the distance from the either edge of the element region. More precisely, the PMOS transistors PM1 and PM5 that are close to the edges of the element region 34, respectively, have higher current-drive efficiencies than the PMOS transistors PM2 to PM4 that are formed in the center part of the element region 34. By contrast, the NMOS transistors NM2 formed in the center part of the element region 35 has higher current drivability than the NMOS transistors NM1 and NM2 that are close to the edges of the element region 35, respectively.
The PMOS transistors and the NMOS transistors differ from one another in terms of operating characteristic, in accordance with the number of the gate electrodes and the positions thereof. The inverter circuit may fail to operate as is desired. The circuit must be redesigned, overcoming such configuration dependency, in order to operate in a desired manner. Alternatively, the circuit must have some design margin set in consideration of the configuration dependency. Even if these measures are taken, however, the circuit will not acquire desirable characteristics, and its design efficiency is low.